W9725G6IB
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
10.20
10.21
10.22
10.23
10.24
10.25
ODT Timing for Active/Standby Mode.................................................................................................66
ODT Timing for Power Down Mode ....................................................................................................66
ODT Timing mode switch at entering power down mode ....................................................................67
ODT Timing mode switch at exiting power down mode ......................................................................68
Data output (read) timing ....................................................................................................................69
Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................69
Data input (write) timing ......................................................................................................................70
Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4)...........................................................70
Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ......................................71
Seamless burst write operation: RL = 5 ( WL = 4, BL = 4).........................................................71
Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) .............................................................72
Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) ..................................................72
Write operation with Data Mask: WL=3, AL=0, BL=4) ...............................................................73
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≦ 2clks) .............74
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≦ 2clks) .............74
Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≦ 2clks) .............75
Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≦ 2clks) .............75
Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP>2clks) ..............76
Burst write operation followed by precharge: WL = (RL-1) = 3 ..................................................76
Burst write operation followed by precharge: WL = (RL-1) = 4 ..................................................77
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≦ 2clks)................77
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP>2clks) .................78
Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≦ 2clks) .......................................................................................78
10.26
Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≦ 2clks) .......................................................................................79
11.
10.27
10.28
10.29
10.30
10.31
10.32
Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3.................................79
Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 .......................80
Self Refresh Timing ...................................................................................................................80
Active Power Down Mode Entry and Exit Timing.......................................................................81
Precharged Power Down Mode Entry and Exit Timing ..............................................................81
Clock frequency change in precharge Power Down mode ........................................................82
PACKAGE SPECIFICATION ..............................................................................................................83
Package Outline WBGA-84 (8x12.5 mm 2 ).......................................................................................................83
12.
REVISION HISTORY ..........................................................................................................................84
Publication Release Date: Oct. 23, 2009
-3-
Revision A04
相关PDF资料
W9725G6JB25I IC DDR2 SDRAM 256MBIT 84WBGA
W9725G6KB-25I IC DDR2 SDRAM 256MBIT 84WBGA
W972GG6JB-3I IC DDR2 SDRAM 2GBITS 84WBGA
W9751G6IB-25 IC DDR2-800 SDRAM 512MB 84-WBGA
W9751G6KB-25 IC DDR2 SDRAM 512MBIT 84WBGA
W9812G6JH-6I IC SDRAM 128MBIT 54TSOPII
W9816G6IH-6I IC SDRAM 16MBIT 50TSOPII
W9825G6JH-6I IC SDRAM 256MBIT 54TSOPII
相关代理商/技术参数
W9725G6JB 制造商:WINBOND 制造商全称:Winbond 功能描述:4M ? 4 BANKS ? 16 BIT DDR2 SDRAM
W9725G6JB-25 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:512MB DDRII
W9725G6JB25I 功能描述:IC DDR2 SDRAM 256MBIT 84WBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C,2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN(2x3) 包装:管件 产品目录页面:1445 (CN2011-ZH PDF)
W9725G6KB-18 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY
W9725G6KB-25 功能描述:IC DDR2 SDRAM 256MBIT 84WBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:4G(256M x 16) 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:48-TFSOP(0.724",18.40mm 宽) 供应商设备封装:48-TSOP I 包装:Digi-Reel® 其它名称:557-1461-6
W9725G6KB-25 TR 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X16
W9725G6KB25A 制造商:WINBOND 制造商全称:Winbond 功能描述:DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
W9725G6KB25I 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:IC DDR2 SDRAM 256M 2.5NS 84WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 256M 2.5NS 84WBGA 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin WBGA